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Description: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。
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Size: 43107 |
Author: 苗苗 |
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Description: EPP和51的接口逻辑Verilog源代码.rar
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Size: 1894 |
Author: 王一木 |
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Description: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send interrupt signals to interrupt the process of writing to read the data in the SRAM. rar package includes epp agreement, modules and test documents (test).
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Size: 43008 |
Author: 苗苗 |
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Description: EPP和51的接口逻辑Verilog源代码.rar-EPP and 51 of the interface logic Verilog source code. Rar
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Size: 2048 |
Author: 王一木 |
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Description: 采用Verilog HDL语言编写的步进电机位置系统，实现步进电机的定速、加速、减速、定位，且速率和加减速度都能做到连续可调的程序，对控制类相关的学习者价值很高-Using Verilog HDL language of the stepper motor position system, stepper motor speed, acceleration, deceleration, positioning, and speed and can do addition and subtraction continuously adjustable speed of the procedure, to control the type of learner-related value high
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Size: 1468416 |
Author: 廖耿耿 |
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Description: 用verilog实现的epp与sram通信的程序-epp communicate with sram in verilog
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Size: 55296 |
Author: chen |
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